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? semiconductor components industries, llc, 2000 november, 2000 rev. 7 1 publication order number: mtsf2p02hd/d mtsf2p02hd preferred device power mosfet 2 amps, 20 volts pchannel micro8 these power mosfet devices are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. they can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. the avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. ? miniature micro8 surface mount package saves board space ? extremely low profile (<1.1mm) for thin applications such as pcmcia cards ? ultra low r ds(on) provides higher efficiency and extends battery life ? logic level gate drive can be driven by logic ics ? diode is characterized for use in bridge circuits ? diode exhibits high speed, with soft recovery ? i dss specified at elevated temperature ? avalanche energy specified ? mounting information for micro8 package provided 2 amperes 20 volts r ds(on) = 90 m d s g 1 8 device package shipping ordering information mtsf2p02hdr2 micro8 4000 tape & reel micro8 case 846a style 1 http://onsemi.com ad marking diagram ww ww = date code source 1 2 3 4 8 7 6 5 top view source source gate drain drain drain drain pin assignment preferred devices are recommended choices for future use and best overall value. pchannel
mtsf2p02hd http://onsemi.com 2 maximum ratings (t j = 25 c unless otherwise noted) negative sign for pchannel devices omitted for clarity rating symbol max unit draintosource voltage v dss 20 v draintogate voltage (r gs = 1.0 m w ) v dgr 20 v gatetosource voltage continuous v gs 8.0 v 1 sq. fr4 or g10 pcb figure 1 below steady state thermal resistance junction to ambient total power dissipation @ t a = 25 c linear derating factor drain current continuous @ t a = 25 c continuous @ t a = 70 c pulsed drain current (note 1.) r thja p d i d i d i dm 70 1.79 14.29 4.5 3.6 36 c/w watts mw/ c a a a minimum fr4 or g10 pcb figure 2 below steady state thermal resistance junction to ambient total power dissipation @ t a = 25 c linear derating factor drain current continuous @ t a = 25 c continuous @ t a = 70 c pulsed drain current (note 1.) r thja p d i d i d i dm 160 0.78 6.25 3.0 2.4 24 c/w watts mw/ c a a a operating and storage temperature range t j , t stg 55 to 150 c 1. repetitive rating; pulse width limited by maximum junction temperature. figure 1. 1 square fr4 or g10 pcb figure 2. minimum fr4 or g10 pcb
mtsf2p02hd http://onsemi.com 3 electrical characteristics (t c = 25 c unless otherwise noted) (note 2.) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (cpk 2.0) (notes 2. & 4.) (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 20 12.7 vdc mv/ c zero gate voltage drain current (v ds = 16 vdc, v gs = 0 vdc) (v ds = 16 vdc, v gs = 0 vdc, t j = 125 c) i dss 0.015 0.03 1.0 25 m adc gatebody leakage current (v gs = 8.0 vdc, v ds = 0) i gss 0.05 100 nadc on characteristics (note 3.) gate threshold voltage (cpk 2.0) (note 4.) (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 0.5 1.1 2.5 1.4 vdc mv/ c static draintosource onresistance (cpk 2.0) (note 4.) (v gs = 4.5 vdc, i d = 2.4 adc) (v gs = 2.7 vdc, i d = 1.2 adc) r ds(on) 70 100 90 120 m w forward transconductance (v ds = 10 vdc, i d = 1.2 adc) (note 2.) g fs 2.6 4.4 mhos dynamic characteristics input capacitance (v 15 vd v 0 vd c iss 550 pf output capacitance (v ds = 15 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss 375 transfer capacitance f = 1 . 0 mhz) c rss 150 switching characteristics (note 4.) turnon delay time t d(on) 10 ns rise time (v ds = 10 vdc, i d = 2.4 adc, t r 27 turnoff delay time (v ds 10 vdc , i d 2 . 4 adc , v gs = 4.5 vdc, r g = 6.0 w ) (note 2.) t d(off) 75 fall time t f 110 turnon delay time t d(on) 22 rise time (v dd = 10 vdc, i d = 1.2 adc, t r 110 turnoff delay time (v dd 10 vdc , i d 1 . 2 adc , v gs = 2.7 vdc, r g = 6.0 w ) (note 2.) t d(off) 55 fall time t f 85 gate charge q t 12.5 18 nc (v ds = 16 vdc, i d = 2.4 adc, q 1 1.5 (v ds 16 vdc , i d 2 . 4 adc , v gs = 4.5 vdc) (note 2.) q 2 6.4 q 3 5.8 sourcedrain diode characteristics forward onvoltage (i s = 2.4 adc, v gs = 0 vdc) (note 2.) (i s = 2.4 adc, v gs = 0 vdc, t j = 125 c) v sd 0.85 0.71 1.0 vdc reverse recovery time t rr 179 ns (i s = 2.4 adc, v gs = 0 vdc, t a 39 (i s 2 . 4 adc , v gs 0 vdc , di s /dt = 100 a/ m s) (note 2.) t b 140 reverse recovery stored charge q rr 0.28 m c 2. pulse test: pulse width 300 m s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperature. 4. reflects typical values. c pk = max limit typ 3 x sigma
mtsf2p02hd http://onsemi.com 4 typical electrical characteristics 2.7 v v gs = 4.5 v t j = 25 c t j = 25 c 2.3 v 2.1 v 1.9 v 3.5 v 4.5 v v gs = 8 v 1.7 v 1.5 v i dss , leakage (na) r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (ohms) 0 0 0.4 1.6 2 0 1 3 v ds , drain-to-source voltage (volts) figure 3. onregion characteristics i d , drain current (amps) i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 4. transfer characteristics 0.05 figure 5. onresistance versus gatetosource voltage i d , drain current (amps) figure 6. onresistance versus drain current and gate voltage 1 100 figure 7. onresistance variation with temperature v ds , drain-to-source voltage (volts) figure 8. draintosource leakage current versus voltage v ds 10 v t j = -55 c 25 c 100 c 4 2 2 4 1 2 2.5 0.5 0.15 01 2 10 0 4 12 16 20 0.09 3 34 r ds(on) , drain-to-source resistance (normalized) t j , junction temperature ( c) -50 0 50 100 150 0 0.5 1.0 1.5 2.0 v gs = 4.5 v i d = 1.2 a 125 75 25 -25 v gs = 0 v t j = 125 c 100 c 1.2 1.5 1 0.11 0.13 1000 0.01 25 c 0.8 0.11 0.13 0.15 0.09 0.05 0.07 24 8 6 1 v gs , gate-to-source voltage (volts) i d = 2.4 a t j = 25 c 0 0.07 5 2.9 v 2.7 v 2.5 v 5 03 35 7 5 0.1 8
mtsf2p02hd http://onsemi.com 5 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 11) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. figure 9. capacitance variation c, capacitance (pf) v ds , drain-to-source voltage (volts) 80812 v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 600 300 0 20 c iss c oss c rss 44 c iss c rss 900 1200 1500 1800 16
mtsf2p02hd http://onsemi.com 6 figure 10. gatetosource and draintosource voltage versus total charge figure 11. resistive switching time variation versus gate resistance v gs , gate-to-source voltage (volts) q g , total gate charge (nc) 03 6 3 9 i d = 2.4 a t j = 25 c v gs 4 1 0 6 5 18 15 9 6 0 v ds q1 q2 12 15 v ds , drain-to-source voltage (volts) t, time (ns) r g , gate resistance (ohms) 1 100 10 10 v dd = 10 v i d = 2.4 a v gs = 4.5 v t j = 25 c t d(on) t r 1000 100 t d(off) t f 3 2 12 q3 qt draintosource diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 13. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 0.5 0.6 0.7 0 0.8 1.2 1.6 v sd , source-to-drain voltage (volts) figure 12. diode forward voltage versus current i s , source current (amps) v gs = 0 v t j = 25 c 0.8 0.9 2.0 0.4 0.3 0.4 2.4
mtsf2p02hd http://onsemi.com 7 i s , source current t, time figure 13. reverse recovery time (t rr ) di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curve (figure 14) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance general data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). figure 14. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 8 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 1 ms 100 m s
mtsf2p02hd http://onsemi.com 8 typical electrical characteristics figure 15. thermal response di/dt t rr t a t p i s 0.25 i s time i s t b figure 16. diode reverse recovery waveform t, time (s) 100 10 1.0 d = 0.5 single pulse 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.2 0.1 0.05 0.02 0.01 1.0e+02 1.0e+03 0.1 1000 r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 rthja(t), effective transient thermal resistance ( c/w)
mtsf2p02hd http://onsemi.com 9 information for using the micro8 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will selfalign when subjected to a solder reflow process. mm inches 0.041 1.04 0.208 5.28 0.015 0.38 0.0256 0.65 0.126 3.20 micro8 power dissipation the power dissipation of the micro8 is a function of the input pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . using the values provided on the data sheet for the micro8 package, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 0.78 watts. p d = 150 c 25 c 160 c/w = 0.78 watts the 160 c/w for the micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.78 watts using the footprint shown. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad . using board material such as thermal clad, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
mtsf2p02hd http://onsemi.com 10 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 17. typical solder heating profile
mtsf2p02hd http://onsemi.com 11 tape & reel information micro8 dimensions are shown in millimeters (inches) feed direction section aa notes: 1. conforms to eia4811. 2. controlling dimension: millimeter. pin number 1 notes: 1. conforms to eia4811. 2. controlling dimension: millimeter. 3. includes flange distortion at outer edge. 4. dimension measured at inner hub. 12.30 4.10 (.161) 11.70 (.484) (.461) 1.85 (.072) 3.90 (.154) 2.05 (.080) 1.95 (.077) bba a 8.10 (.318) 7.90 (.312) 5.55 (.218) 5.45 (.215) 1.65 (.065) 1.60 (.063) 1.50 (.059) 1.60 (.063) 1.50 (.059) typ. 0.35 (.013) 0.25 (.010) 3.50 (.137) 3.30 (.130) 1.50 (.059) 1.30 (.052) section bb 5.40 (.212) 5.20 (.205) 330.0 (13.20) max. 50.0 (1.97) min. 14.4 (.57) 12.4 (.49) note 4 18.4 (.724) max. note 3 13.2 (.52) 12.8 (.50)
mtsf2p02hd http://onsemi.com 12 package dimensions style 1: pin 1. source 2. source 3. source 4. gate 5. drain 6. drain 7. drain 8. drain s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. b a d k g pin 1 id 8 pl 0.038 (0.0015) t seating plane c h j l micro8 case 846a02 issue e on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mtsf2p02hd/d micro8 is a trademark of international rectifier. thermal clad is a registered trademark of the bergquist company. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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